A nonvolatile memory device of a structure as shown in FIG. 10 has been proposed for application to a tuning switch of an integrated circuit according to a conventional technology (see Patent Literature 1). This nonvolatile memory device is a single-layer polysilicon structure, and can be prepared by a standard CMOS process. However, such a device has been proposed as a cell to be incorporated into a nonvolatile memory array. The memory array is effective for an application requiring memory exceeding 1 Kbits, but peripheral circuits surrounding the array are large-sized. Thus, the memory array is inconvenient to use for an application that does not require such large number of memories.